1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to a transistor suitable for use in integrated circuit devices having small feature sizes.
2. Description of the Prior Art
As semiconductor integrated circuits continue to become smaller, it becomes increasingly difficult to fabricate transistors which operate reliably and predictably. As device feature sizes shrink to dimensions well below one micron, transistors become strongly affected by short channel effects.
Short channel effects occur as a result of the voltage field at the drain. Since the channel is very short, the electric fields from both the gate and drain affect the flow of current through the channel, changing operation of the transistor from the desired parameters. If the drain electric field is strong enough, the depletion region can extend all the way to the source, resulting in punch through.
Short channel effects can mostly be negated by increasing the dopant concentration in the channel region. However, undesirable side effects occur as a result of increasing the dopant concentration. Carrier mobility is degraded, lowering transistor gain, and threshold voltage (V.sub.t) is increased.
It would be desirable to provide a transistor structure, and method for making same, which provides improved avoidance of short channel effects without unduly adversely affecting transistor operating characteristics. It would be further desirable for such a structure and method to be compatible with widely available fabrication techniques.